Cache Explorer
Follow array[i] += 1 through repeated passes. Change the array and stride, then watch whole lines move into the cache and individual bytes change.
Memory array
Each row is one memory block. Cells show byte offset above, stored value below. Green rows have a copy in cache.
Cache contents
| Set | Way | Block / tag | Bytes: offset / value | State |
|---|
Dirty = modified in cache. Memory receives the changed line when it is evicted. LRU replaces the least recently used line within its set.
Accesses
Every pass restarts at offset 0. Changing any cache or array setting starts a fresh experiment.
Results so far
What to try, and what this model means
Spatial reuse: use a 32-byte array, a 16-byte cache, 4-byte lines and stride 1. Each loaded line supplies four updates: one miss followed by three hits. Change the stride to 4: each update uses a new line.
Temporal reuse and capacity: reduce the array to 16 bytes. After the first pass, the full array fits and subsequent passes hit. Increase it to 32 bytes with stride 4: the lines continually replace one another.
The sharp drop: the set-conflict preset uses a 32-byte array, a 16-byte cache, 4-byte lines, two ways and stride 8. Blocks 0, 2, 4 and 6 all select set 0, which holds only two lines. Then try the fewer-competing-lines preset: stride 16 visits only blocks 0 and 4, so both remain cached after the first pass. The cache capacity has not changed.
Organisation: direct mapped means one line per set; a 2-way cache holds two lines per set; a fully associative cache has one set containing all its lines. Mapping here is block number modulo number of sets.
Teaching model: one byte per array element, one cache level, aligned array starting at address 0, write allocate, write back, LRU replacement and an initially empty cache. Values wrap after 255. It models hits and misses, not execution time. It omits prefetching, TLBs, instruction execution and overlap between memory operations. These are illustrative sizes, not a model of the M2 Max. Your benchmark warms up before timing; later passes here demonstrate that reuse.